Replicating an RF Probe Based on Bob Pease's Design

Why Do We Need a High-Impedance Probe with Low Input Capacitance?

To measure the resonant frequency of parallel resonant circuits, the voltage across the circuit must be measured with the highest possible impedance. This is because a parallel resistance degrades the quality factor \(\text{Q factor}\), and a parallel capacitance alters the resonant frequency. At high frequencies, input capacitance becomes the dominant factor. A standard 10:1 oscilloscope probe with an input impedance of \( 10M \Omega /18pF \) has a capacitive input impedance of approximately \( 884 \Omega \) at \(10\text{ MHz}\). Therefore, to achieve accurate measurements, active probes with input capacitances below \(5\text{ pF}\) are typically used. However, the lower the input capacitance, the more expensive these active probes become.

While searching for circuit designs suitable for a DIY project, I came across a proposal by Bob Pease. Bob was a brilliant analog designer at National Semiconductor and is introduced on page 3 of the article series linked below. He influenced generations of engineers with his practical approaches and remains a prime source of analog know-how to this day.

The legend, Bob Pease.

In this article series the RF probe is introduced on page 12 of the PDF. This circuit has been virtually the standard for DIY RF probes for decades. However, some of the transistors originally used by Bob are no longer available. Nonetheless, I decided to give the replication a try. In parallel, I simulated the circuit in LTspice to better understand its constraints and the impact of various components.

RF probe based on Bob Pease's design.

Simulation schematic in LTspice.

Construction

Due to the high frequencies involved, I chose the "dead-bug" prototyping method.

"Dead-bug" construction—top view.

"Dead-bug" construction—bottom view.

Simulation

The download link for the LTspice schematic can be found at the end of this blog post.
The best way to evaluate the circuit's performance is by analyzing its frequency response. An \(S_{21}\) measurement using a VNA (Vector Network Analyzer) is ideal for this purpose. I have a LiteVNA 64 available for my tests.
When measuring \(S_{21}\), it is crucial to note that both the VNA output and input are terminated with \(50\ \Omega\). For the high-impedance input of the RF probe, the \(50\ \Omega\) source impedance has (almost) no impact. However, the probe's output is heavily loaded by the VNA's \(50\ \Omega\) input. The output impedance of a common-collector circuit (emitter follower) is roughly \(26\ \Omega\), depending on current and temperature. This forms a voltage divider. While the voltage gain is nearly 1 (0 dB) when measured with a high-impedance load, it drops significantly under a \(50\ \Omega\) load. This is precisely what the simulation is intended to illustrate.
An example of how to set up an \(S_{21}\) simulation can be found directly within LTspice (C:\Users\...\AppData\Local\LTspice\examples\Educational\S-param.asc). The command .net I(R7) V3 generates the S-parameters, which can then be added to a plot using "Add Traces to Plot".
The \(S_{21}\) measurement with the VNA inherently yields a reading that is 6 dB too low.

Because the VNA internally assumes a \(50\ \Omega\) load, but the open-circuit source voltage is twice as high as the voltage under load, a systematic measurement error occurs in \(S_{21}\).

For \( Z_{in} \gg 50\ \Omega \), this results in an offset of approximately -6 dB. Therefore, a measured value of +6 dB actually corresponds to a real voltage gain (\(v_u\)) of 0 dB (unity gain). Consequently, to determine the cutoff frequency from the plot, you need to find the point that is 3 dB below the low-frequency gain.

\(S_{21}\) simulated with LTspice. Click image for details..

The cutoff frequency determined via this method was just under \( 84MHz \).

Measurement with the LiteVNA 64

To measure \(S_{21}\) correctly with the VNA, the SOLT (Short/Open/Load/Through) calibration must be performed in the frequency range of interest (approx. 1 to 100 MHz) as follows:

• Port 1: Leave disconnected (no cable).
• Port 2: Connect a test cable.
• Connect the Short/Open/Load calibration standards directly to Port 1.
• Connect the test cable from Port 2 to Port 1 for the Through calibration.

This calibrates the path between Port 1 (without a cable) and Port 2 (with a cable). To measure the RF probe, the input needle is inserted directly into the center pin of Port 1, and the probe's coaxial output cable is connected to the test cable from Port 2.

\(S_{21}\) measured with the LiteVNA 64. Click image for details.

The cutoff frequency measured with the LiteVNA 64 was just under \( 28MHz \).

Impact of Stray Capacitances

The transistor capacitances are already included in the LTspice models.
While the "dead-bug" layout offers distinct advantages regarding shielding and noise immunity (thanks to the solid ground plane on the reverse side), its main disadvantage is that every component "island" forms a parasitic capacitance to ground. Additionally, stray capacitances form between the islands themselves. These are not accounted for in the default LTspice simulation. To model this, I set up a worst-case simulation featuring four such stray capacitances.
An estimation using the parallel-plate capacitor formula yields the following value for a \(2.5 \times 2.5\text{ mm}\) island:

• \( A \text{ Area}\)
• \( \epsilon_0 = 8.854 \cdot 10^{-12} \text{ F/m (Vacuum permittivity)} \)
• \( \epsilon_r \text{ Relative permittivity of FR4 4.7}\)
• \( D \text{ PCB thickness, 1.6mm}\)

To account for fringing fields, a common method is to include the sidewalls of the island in the total area calculation:

• \( A \text{ Area}\)
• \( l \text{ Length of the island} \)
• \( b \text{ Width of the island}\)
• \( h \text{ Copper thickness \(35 \mu \)m}\)

For a \(2.5 \times 2.5\text{ mm}\) island, this calculation results in a capacitance of \(0.172\text{ pF}\), which is relatively low

Simulation including parasitic capacitances..

\(S_{21}\) with parasitic capacitances. Click image for details.

In the simulation, I assumed a stray capacitance of \(2\text{ pF} \pm 1.5\text{ pF}\) (ranging from \(0.5\) to \(3.5\text{ pF}\)) at each node. This is significantly higher than the calculated value. Even so, the simulated frequency response only dropped from 84 MHz to 53 MHz—nowhere near the measured 28 MHz.
Does anyone have an idea why the real-world frequency response is so much worse than simulated?